Stacked inductors and transformers in CMOS technology

By A. Zolfaghari, Andrew Chan, B. Razavi. IEEE J. Solid State Circuits, 2001

368 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/8bb9e923b16b8869a30ef97ce7b1d5a15b397a71

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Citations in the corpus

• 30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits (2005, background): “The effective inductor quality factor is extracted as (2) It is noted that attempts to implement stacked inductors at lower frequencies (below 10 GHz) have resulted in low quality factors, on the order of 2–3 [11] due to additional via resistance.”
• Lumped Elements for RF and Microwave Circuits (2003, methodology): “Here for two-layer and multilayer structures, the expressions for Ceq are given by [42] Ceq = 1 12 (4C1 + C2 ) two-layer (3.”
• A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors (2008, background): “The low resistance requirement immediately rules out the series-connected, stacked inductor geometry for this application, which initially looked promising due its high inductance property [12].”