Register allocation and spilling via graph coloring

By Gregory J. Chaitin. SIGP, 2004

320 citations recorded by the source corpus.

Subfields: Computer Science Applications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/7706d70d9c8a6ea5842b428220bcabca429ffbad

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Science Applications

1. Xavier Leroy

In Hardware and Architecture

1. Xavier Leroy

Citations in the corpus

• Formal certification of a compiler back-end or: programming a compiler with a proof assistant (2006, methodology): “The register allocator is based on coloring of an interference graph, in the style of Chaitin [7], using the George-Appel [12] heuristic for graph coloring and coalescing.”
• A Formally Verified Compiler Back-end (2009, methodology): “Based on the results of liveness analysis, an interference graph is built following Chaitin’s construction [20].”
• Formal verification of a realistic compiler (2009, methodology): “An interference graph having pseudo-registers as nodes is then built following Chaitin’s rules [6], and proved to contain all the necessary interference edges.”