Metrology for the next generation of semiconductor devices

By N. Orji, M. Badaroglu, B. Barnes, C. Beitia, B. Bunday, U. Celano, R. J. Kline, M. Neisser, Y. Obeng, A. E. Vladár. Nature Electronics, 2018

461 citations recorded by the source corpus.

The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution. This Review Article examines state-of-the-art metrology methods for integrated circuits and highlights how new integrated circuit device design and industry requirements affect lithography options and consequently metrology requirements.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/6ec358a52670b82f62ebeaf3df54c61b6d9ed8f9

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Citations in the corpus

• An insight into optical metrology in manufacturing (2020, unknown): “State-of-the-art optical scatterometry at the near-atomic scale faces severe challenges of insufficient sensitivity and terrible parameter correlation [290, 291].”
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