Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

By P. Morrow, Chang-min Park, Shriram Ramanathan, M. Kobrinsky, M. Harmes. IEEE Electron Device Letters, 2006

169 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/6e01c84ea83031584f2b7fccf5296d1de8179ef5

Citations in the corpus

• A study of thermo-mechanical stress and its impact on through-silicon vias (2008, unknown): “Devices may be stacked by chip-to-chip (chiplevel stacking) [2], wafer-to-wafer (wafer-level stacking) [3] or chip-to-wafer bonding [4] methods.”