Transaction level modeling: an overview

By Lukai Cai, D. Gajski. First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721), 2003

646 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/6c6101bd01e7eea0c344939361ce11c5ea83bca3

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Cagkan Erbas
2. Simon Polstra
3. Andy D. Pimentel

In Hardware and Architecture

1. Cagkan Erbas
2. Simon Polstra
3. Andy D. Pimentel

Citations in the corpus

• Hardware implementation of memristor-based artificial neural networks (2024, neutral): “Given their customization capabilities, TLM can be divided into different categories as indicated by Gai et al. 237 (see Fig.”
• A systematic approach to exploring embedded system architectures at multiple abstraction levels (2006, background): “Architecture models in Sesame, which typically operate at the so-called transaction level [41], [42], simulate the performance consequences of the computation and communication events generated by an application model.”