Intel ® 64 and IA-32 Architectures Software Developer ’ s Manual

By No License, Intel Disclaims. 2006

338 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/6c359635836b4caf30fdec0153b6aea210833d41

Citations in the corpus

• Estimation of energy consumption in machine learning (2019, unknown): “Intel Power Gadget uses the Intel RAPL interface [31] to provide power and energy estimations of the core and uncore of the”
• A minimalist approach to Remote Attestation (2014, unknown): “However, this argument is incorrect, for the following reasons: First, in some instruction sets (e.g, Intel x86 [11]), skipping the first byte(s) of an instruction can lead to decoding a different instruction.”
• Heracles: Improving resource efficiency at scale (2015, unknown): “For LLC isolation, Heracles uses the Cache Allocation Technology (CAT) available in recent Intel chips (hardware mechanism) [3].”
• QSYM : A Practical Concolic Execution Engine Tailored for Hybrid Fuzzing (2018, unknown): “, the amd64 ISA) contains 1,795 instructions [13] described in a 2,000-page manual [14].”
• Detecting Privileged Side-Channel Attacks in Shielded Execution with Déjà Vu (2017, unknown): “This abort is enforced in hardware; even the most privileged system software cannot avoid it [1].”