High-speed architectures for Reed-Solomon decoders
By D. Sarwate, Naresh R Shanbhag. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2001
318 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/6c01e8629d0cbfda896fce03a6e2c5f0396bc92d
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In Artificial Intelligence
In Electrical and Electronic Engineering
Citations in the corpus
- PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator (2012, background): “If Λ evaluates to zero for αi then the corresponding error bit enBCH−i = 1.”