A Portable Programming Interface for Performance Evaluation on Modern Processors
By S. Browne, Jack J. Dongarra, N. Garner, George Ho, P. Mucci. The international journal of high performance computing applications, 2000
773 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/6a370f3168b640dee3d1c7daf3ac2e7662766760
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- J. Demmel
- Oded Schwartz
- Daniel Terpstra
- Haihang You
- Heike Jagode
- Shoaib Kamil
- Armando Fox
- Jack J. Dongarra
In Hardware and Architecture
- J. Demmel
- Oded Schwartz
- Daniel Terpstra
- Haihang You
- Heike Jagode
- Shoaib Kamil
- Sameer Suresh Shende
- Allen D. Malony
Citations in the corpus
- The Tau Parallel Performance System (2006, background): “TAU supports different timing sources, choice of hardware counters through the PAPI (Browne et al. 2000) or PCL (Berrendorf, Ziegler, and Mohr) interfaces, and access to system performance data.”
- On the Detection of Kernel-Level Rootkits Using Hardware Performance Counters (2017, methodology): “Finally, there are many libraries and software toolkits available for accessing HPCs, such as [3, 5] and [13].”
- Communication-Optimal Parallel Recursive Rectangular Matrix Multiplication (2013, methodology): “Figure 3 shows the number of level 3 cache misses for CARMA and for MKL on m = n = 64, k = 524288, a case where CARMA is significantly faster, obtained using the Performance Application Programming Interface (PAPI [18]).”
- Collecting Performance Data with PAPI-C (2009, methodology): “The use of hardware counters to measure and improve software performance has become an accepted and integral method in the software development cycle [1].”