Analysis of high-performance floating-point arithmetic on FPGAs

By G. Govindu, Ling Zhuo, S. Choi, Viktor K. Prasanna. 2004

167 citations recorded by the source corpus.

Subfields: Computational Theory and Mathematics, Electrical and Electronic Engineering, Hardware and Architecture

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computational Theory and Mathematics

1. Matthieu Courbariaux
2. Yoshua Bengio
3. Vikas Sindhwani
4. Tara N. Sainath

In Electrical and Electronic Engineering

1. Yoshua Bengio
2. Matthieu Courbariaux

In Hardware and Architecture

1. Matthieu Courbariaux
2. Yoshua Bengio

Citations in the corpus

• BinaryNet: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1 (2016, background): “For instance, a 32-bit floating point multiplier costs about 200 FPGA slices (Govindu et al., 2004; Beauchamp et al., 2006), whereas a 1-bit XNOR gate only costs a single slice.”
• Towards Accurate Binary Convolutional Neural Network (2017, background): “For instance, a 32-bit floating point multiplier costs about 200 Xilinx FPGA slices [Govindu et al., 2004], whereas a 1-bit xnor gate only costs a single slice.”