Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures

By R. M. Incandela, Lin Song, H. Homulle, E. Charbon, A. Vladimirescu, F. Sebastiano. IEEE Journal of the Electron Devices Society, 2018

228 citations recorded by the source corpus.

Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16- $\mu \text{m}$ and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device dc characteristics, the accuracy and validity of the compact models are demonstrated by comparing time- and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/586a4e43947b7a75f4d15f159483ee56cd01f3f3

Citations in the corpus

• Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors (2020, unknown): “2 K [1]–[6], ≈ 9 mV/dec instead of 20 μV/dec at 100 mK [7], and ≈ 7 mV/dec instead of 4 μV/dec at 20 mK [8].”