Real-time dynamic voltage scaling for low-power embedded operating systems
By Padmanabhan Pillai, Kang G. Shin. Symposium on Operating Systems Principles, 2001
1,377 citations recorded by the source corpus.
Subfields: Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/4ed50ef3ebdc06a2a4480f7a49a5403515862ea6
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Hardware and Architecture
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- Parthasarathy Ranganathan
- Sarma B. K. Vrudhula
- Benjamin Gaudette
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- Pedro Mejía-Alvarez
- Hakan Aydin
- H. Hoffmann
Citations in the corpus
- Power-aware scheduling for periodic real-time tasks (2004, methodology): “Shin et al. [26] proposed an intratask DVS framework for aperiodic real-time tasks with (possibly) precedence constraints .”
- ECOSystem: managing energy as a first class operating system resource (2002, background): “The term "throttling" (which we have used in a very general sense) is most often associated with the growing literature on voltage/clock scheduling [24, 25, 13, 33, 12, 34, 16, 9, 27, 26] for processors that support dynamic voltage scaling.”
- JouleSort: a balanced energy-efficiency benchmark (2007, background): “These costs vary depending upon the installation, but they are growing rapidly and have the potential eventually to outstrip the cost of hardware [2].”
- A framework of energy efficient mobile sensing for automatic user state recognition (2009, background): “The problem of energy management on mobile devices has been well-explored in the literature such as [28, 29, 30, 31, 32].”
- The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction (2003, neutral): “[37] P. Pillai and K. Shin.”
- Power Aware Scheduling of Bag-of-Tasks Applications with Deadline Constraints on DVS-enabled Clusters (2007, background): “Many studies have been done on DVS real-time scheduling on single processor systems [19, 20, 23].”
- Energy Efficient Mobile Cloud Computing Powered by Wireless Energy Transfer (2015, background): “Another energy-efficient approach is to control the CPU-cycle frequencies under the deadline constraint by exploiting the fact that lowering the frequencies reduces the energy consumption [15]–[17].”
- Scheduling with dynamic voltage/speed adjustment using slack reclamation in multi-processor real-time systems (2001, background): “4 ms to change volt age and 40 s to change frequency [22].”
- Environment-conscious scheduling of HPC applications on distributed Cloud-oriented data centers (2011, background): “…are generally composed of CMOS circuits is given by: P = αV 2 f + I leak V + P short , where P is the power dissipation, V is the supply voltage, f is the clock frequency, I leak is the leakage current, and P short is the short circuit power dissipated during the voltage switching process [8] [48].”
- Cyber–Physical Systems: A Perspective at the Centennial (2012, background): “resource reservation for real-time applications, in [160]– [162] on a control theoretical approach to performance and throughput management of computing systems, in [163] on real-time scheduling algorithms for power management in Kim and Kumar: Cyber–Physical Systems: A Perspective at the Centennial”
- Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee (2016, background): “From this perspective, it is imperative to ensure user satisfaction even at the cost of additional power; however, due to finite energy capacity, it is not typically optimal for mobile platforms to sustain high performance states, and as this paper will demonstrate, providing guarantees on QoS…”
- Managing performance vs. accuracy trade-offs with loop perforation (2011, background): “Moreover, for real-time computations, loop perforation may free up the time required to enable additional synergistic energy-saving optimizations such as voltage scaling [28].”
- DORA: Optimizing Smartphone Energy Efficiency and Web Browser Performance under Interference (2018, background): “predict and operate processors at an optimal energy-efficient setting [21]–[31] but also allows designs to control the degree of memory interference experienced in a multiprogrammed setting [32]–[35].”