Transaction Level Modeling with SystemC

By Frank Ghenassia. 2005

372 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/4d93e6d3f37625dcee70502d7ed65e0571114fc3

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Alberto L. Sangiovanni-Vincentelli
2. Radu Mateescu
3. Hubert Garavel
4. Wendelin Serwe
5. Frédéric Lang

In Hardware and Architecture

1. Alberto L. Sangiovanni-Vincentelli
2. Radu Mateescu
3. Hubert Garavel
4. Wendelin Serwe
5. Frédéric Lang
6. Rajeev Alur

Citations in the corpus

• CADP 2011: a toolbox for the construction and analysis of distributed processes (2012, positive): “Regarding the graph module, only Lotos was supported at first, but support for more languages (Fsp [90], Lotos NT [13], μCrl [66], Sdl [78], and SystemC/Tlm [112]), more automata-based formalisms (Bcg, Exp [84], Fc2 [9], and Seq [50]) and more external tools (If [11], Kronos [128], Ltsmin [7], TorX ”
• Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design (2007, background): “F. Ghenassia of ST Microelectronics, one of the most vocal and competent proposers of this style of design capture and analysis [93] estimates by using measurements on actual ST designs that high-level TLM can provide a factor of three orders of magnitude improvement in terms of simulation speed…”