Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers
By Prakash Murali, Jonathan M. Baker, Ali Javadi-Abhari, Frederic T. Chong, Margaret Martonosi. International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
495 citations recorded by the source corpus.
A massive gap exists between current quantum computing (QC) prototypes, and the size and scale required for many proposed QC algorithms. Current QC implementations are prone to noise and variability which affect their reliability, and yet with less than 80 quantum bits (qubits) total, they are too resource-constrained to implement error correction. The term Noisy Intermediate-Scale Quantum (NISQ) refers to these current and near-term systems of 1000 qubits or less. Given NISQ's severe resource constraints, low reliability, and high variability in physical characteristics such as coherence time or error rates, it is of pressing importance to map computations onto them in ways that use resources efficiently and maximize the likelihood of successful runs. This paper proposes and evaluates backend compiler approaches to map and optimize high-level QC programs to execute with high reliability on NISQ systems with diverse hardware characteristics. Our techniques all start from an LLVM intermediate representation of the quantum program (such as would be generated from high-level QC languages like Scaffold) and generate QC executables runnable on the IBM Q public QC machine. We then use this framework to implement and evaluate several optimal and heuristic mapping methods. These methods vary in how they account for the availability of dynamic machine calibration data, the relative importance of various noise parameters, the different possible routing strategies, and the relative importance of compile-time scalability versus runtime success. Using real-system measurements, we show that fine grained spatial and temporal variations in hardware parameters can be exploited to obtain an average 2.9x (and up to 18x) improvement in program success rate over the industry standard IBM Qiskit compiler. Despite small qubit counts, NISQ systems will soon be large enough to demonstrate "quantum supremacy", i.e., an advantage over classical computing. Tools like ours provide significant improvements in program reliability and execution time, and offer high leverage in accelerating progress towards quantum supremacy.
Subfields: Artificial Intelligence, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/4d83d4b005c6041d069ca6316052d388450ebab9
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Artificial Intelligence
- Song Han
- Yujun Lin
- David C. McKay
- Hanrui Wang
- Ali Javadi-Abhari
- Margaret Martonosi
- Prakash Murali
- Jay M. Gambetta
In Hardware and Architecture
- Ali Javadi-Abhari
- Song Han
- David Zhigang Pan
- Margaret Martonosi
- Jay M. Gambetta
- Hanrui Wang
- Yujun Lin
- Yonggang Wen
Citations in the corpus
- QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits (2021, methodology): “Noise-adaptive qubit mapping [34], [48], [58] aims to find the best mapping from logical qubits to physical qubits, which minimizes the gate error and SWAP insertion overhead.”
- Software Mitigation of Crosstalk on Noisy Intermediate-Scale Quantum Computers (2020, methodology): “tes, the compilation time is less than 2 minutes. Even with 1000 gates, the compile times are under 15 minutes. These execution times can be easily improved with known optimizations for SMT compilers [43, 44]. This evaluation gives us confidence that our methods will be practical even on large NISQ-”
- t|ket⟩: a retargetable compiler for NISQ devices (2020, background): “There are also promising results for using information on the noise characteristics and fidelities of the target device to assist compilation [40, 41, 42].”
- Quantum computing with Qiskit (2024, methodology): “This includes novel methods for circuit transformation and resource optimization [12, 32, 44, 47, 55, 63, 67, 90, 97, 103], using pulse and timing capabilities for error suppression or enablement of new gates [28, 36, 66, 68, 84, 98], or high-level language design and formal compiler verification…”