Modeling and sizing for minimum energy operation in subthreshold circuits

By Benton H. Calhoun, Alice Wang, Anantha P. Chandrakasan. IEEE Journal of Solid-State Circuits, 2005

575 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/4c9165729bf3bc70896c904bbd8eb839a9fb9b11

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Jan M. Rabaey
2. Anantha P. Chandrakasan
3. Massimo Alioto
4. Ian F. Akyildiz
5. Mohamed F. Younis
6. Xuxun Liu
7. Deborah Estrin
8. Alper Erturk

Citations in the corpus

• Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits (2008, background): “Proper logic styles and device sizing ensure functional logic gates for a desired yield, while long logic paths provide an averaging effect similar to device upsizing, which reduces the statistical spread of propagation delays.”
• Ultralow-Power Design in Near-Threshold Region (2010, background): “Based on these observations, subthreshold digital logic design has gained quite some attention over the past few years [ 9 ], [10].”