The Art of Analog Layout

By A. Hastings. 2000

823 citations recorded by the source corpus.

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A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique (2004, background): “As a result, the relationship between the output current and the sensing current does not depend on the exact values of the resistors and , but on their ratio, which can be easily controlled with analog layout techniques [25].”
A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS (2006, background): “However, in this prototype, the ratio is noninteger, which significantly increases layout complexity and matching difficulty [15] for a full array.”
A 300 nW, 15 ppm/$^{\circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs (2009, background): “It can be reduced by using large-sized transistors and various analog layout techniques [21], [22].”
A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference (2011, background): “Careful layout techniques [19] and large transistor [20], can help to reduce those effects.”
Fully integrated wideband high-current rectifiers for inductively powered devices (2004, background): “To decrease the risk of latch-up even further, the pMOS complexes and the nMOS pair are widely separated in the layout and protected by N and P guard rings, respectively [19].”
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC (2007, background): “plate routing is separated from the capacitors by grounded metal [ 25 ].”