Leakage in Nanometer CMOS Technologies

By S. Narendra, Anantha P. Chandrakasan. 2010

249 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/43ae0f2766b3da09a6fe36f1750a87e7218b7b74

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In Electrical and Electronic Engineering

1. Massimo Alioto
2. G. Iannaccone

Citations in the corpus

• Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial (2012, methodology): “Unfortunately, in subthreshold power gating is less effective than above threshold for various reasons, as discussed in the following assuming that a header transistor is used [14].”
• A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference (2011, background): “in which summarizes the product between the aspect ratio and the process and temperature parameters found in (1) and is the drain-induced barrier lowering (DIBL) factor [18].”