Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge

By Efraim Rotem, Alon Naveh, Avinash Ananthakrishnan, Eli Weissmann, Doron Rajwan. IEEE Micro, 2012

495 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/3ee47780011ee618bd5a64624a662375e1958e0a

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Gu-Yeon Wei
2. David M. Brooks

In Hardware and Architecture

1. Gu-Yeon Wei
2. David M. Brooks
3. Kim M. Hazelwood
4. Abhishek Dhanotia
5. Akshitha Sriraman

Citations in the corpus

• Tradeoffs between power management and tail latency in warehouse-scale applications (2014, background): “In the first one, idle power states (C-states), decrease core power when no threads have claimed a core and it is executing the operating system idle loop.”