Tile size selection using cache organization and data layout

By S. Coleman, Kathryn S. McKinley. 1995

Subfields: ML Systems & Hardware

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In ML Systems & Hardware

1. G. Diamos
2. Newsha Ardalani
3. Joel Hestness

Citations in the corpus

• Beyond human-level accuracy: computational challenges in deep learning (2019, background): “We capture the impact of cache hierarchy on performance by modeling these extra memory accesses, assuming a common, tiled matrix multiply implementation [12].”
• Automatic performance tuning of sparse matrix kernels (2003, unknown): “For cache optimizations, a variety of sophisticated static models have been developed for kernels like matrix multiply to help understand cache behavior, to predict optimal tile sizes, and to transform loops to improve temporal locality [119, 131, 202, 331, 71, 220, 81, 67, 68].”