Foundations of the C++ concurrency memory model
By H. Boehm, Sarita V. Adve. ACM-SIGPLAN Symposium on Programming Language Design and Implementation, 2008
518 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/29ead6d3bd248b6845a6d311a4d92f629c87fbd6
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- T. Harris
- J. Larus
- Ravi Rajwar
- Peter Sewell
- Michael Lee Scott
- Michael F. Spear
- Dhruva R. Chakrabarti
- Luke Dalessandro
In Hardware and Architecture
- T. Harris
- J. Larus
- Ravi Rajwar
- Peter Sewell
- Michael Lee Scott
- Michael F. Spear
- Dhruva R. Chakrabarti
- Luke Dalessandro
Citations in the corpus
- Mathematizing C++ concurrency (2011, methodology): “[BA08] H.-J. Boehm and S.V. Adve.”
- NOrec: streamlining STM by abolishing ownership records (2010, background): “In other memory models (e.g., that of C++ [ 3 ]), program behavior in the presence of a data race is undefined.”
- Atlas (2014, methodology): “Instead of tracking write-read dependency at the memory access level, we use an ordering on entire FASEs induced by the happensbefore relation [4, 13], to capture the durability constraints.”
- Transactional Memory, 2nd edition (2010, background): “The emerging C/C++ memory model has catch-fire semantics for races in lock-based programs [43], and so it might be reasonable to follow this approach in programs using transactions.”
- A Better x86 Memory Model: x86-TSO (2009, background): “They allow independent readers to see independent writes (by different processors to different addresses) in different orders, as below (IRIW, see also [6]), but require that, in some sense, causality is respected: “P5.”