Embedded floating-point units in FPGAs

By Michael J. Beauchamp, Scott Hauck, K. Underwood, K. Hemmert. 2006

83 citations recorded by the source corpus.

Subfields: Computational Theory and Mathematics, Electrical and Electronic Engineering, Hardware and Architecture, ML Systems & Hardware

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computational Theory and Mathematics

1. Matthieu Courbariaux
2. Ran El-Yaniv
3. Yoshua Bengio
4. Daniel Soudry
5. Itay Hubara
6. Vikas Sindhwani
7. Tara N. Sainath

In Electrical and Electronic Engineering

1. Ran El-Yaniv
2. Yoshua Bengio
3. Daniel Soudry
4. Matthieu Courbariaux
5. Itay Hubara

In Hardware and Architecture

1. Matthieu Courbariaux
2. Yoshua Bengio

In ML Systems & Hardware

1. Matthieu Courbariaux
2. Ran El-Yaniv
3. Yoshua Bengio
4. Daniel Soudry
5. Itay Hubara

Citations in the corpus

• Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations (2016, background): “For instance, a 32-bit floating point multiplier costs about 200 Xilinx FPGA slices (Govindu et al., 2004; Beauchamp et al., 2006), whereas a 1-bit XNOR gate only costs a single slice.”