Reversible hysteresis inversion in MoS2 field effect transistors

By Naveen Kaushik, D. Mackenzie, Kartikey Thakar, Natasha Goyal, Bablu Mukherjee, Peter Bøggild, D. H. Petersen, S. Lodha. npj 2D Materials and Applications, 2017

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The origin of threshold voltage instability with gate voltage in MoS2 transistors is poorly understood but critical for device reliability and performance. Reversibility of the temperature dependence of hysteresis and its inversion with temperature in MoS2 transistors has not been demonstrated. In this work, we delineate two independent mechanisms responsible for thermally assisted hysteresis inversion in gate transfer characteristics of contact resistance-independent multilayer MoS2 transistors. Variable temperature hysteresis measurements were performed on gated four-terminal van der Pauw and two-terminal devices of MoS2 on SiO2. Additional hysteresis measurements on suspended (~100 nm air gap between MoS2 and SiO2) transistors and under different ambient conditions (vacuum/nitrogen) were used to further isolate the mechanisms. Clockwise hysteresis at room temperature (300 K) that decreases with increasing temperature is shown to result from intrinsic defects/traps in MoS2. At higher temperatures a second, independent mechanism of charge trapping and de-trapping between the oxide and p+ Si gate leads to hysteresis collapse at ~350 K and anti-clockwise hysteresis (inversion) for temperatures >350 K. The intrinsic-oxide trap model has been corroborated through device simulations. Further, pulsed current–voltage (I–V) measurements were carried out to extract the trap time constants at different temperatures. Non-volatile memory and temperature sensor applications exploiting temperature dependent hysteresis inversion and its reversibility in MoS2 transistors have also been demonstrated.MoS 2 devices: variable temperature measurements unveil reversible hysteresis mechanismsDefects and traps in MoS2 van der Pauw devices give rise to a hysteresis inversion mechanism which is reversible with temperature. A team led by Saurabh Lodha at the Indian Institute of Technology Bombay performed variable temperature hysteresis measurements on four- and two-terminal MoS2 devices, both suspended and supported on a SiO2 substrate. The onset of a clockwise hysteresis at room temperature was attributed to intrinsic MoS2 defects, whereas an additional mechanism resulting in an anticlockwise hysteresis was observed at higher temperature, and attributed to extrinsic charge trapping and de-trapping between the oxide and the silicon gate. By leveraging the temperature dependence of the hysteresis in MoS2, the authors developed a non-volatile memory and a temperature sensor.

Subfields: Electrical and Electronic Engineering, Materials Chemistry

View Paper: https://www.semanticscholar.org/paper/233570d71e475dd9850670c147e8350baa141e83

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Citations in the corpus

Electrical characterization of 2D materials-based field-effect transistors (2020, methodology): “(g) Schematic of a multilayer MoS2 device with van der Pauw contact configuration [71].”