Demystifying GPU microarchitecture through microbenchmarking
By Henry Wong, Misel-Myrto Papadopoulou, Maryam Sadooghi-Alvandi, Andreas Moshovos. IEEE International Symposium on Performance Analysis of Systems and Software, 2010
490 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/23177452df15b652dd54a59324502b92c99687a7
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Onur Mutlu
- Saugata Ghose
- Rachata Ausavarungnirun
- Adwait Jog
- Mahmut Taylan Kandemir
- Christopher J. Rossbach
- Timothy G. Rogers
- Jayneel Gandhi
In Hardware and Architecture
- Onur Mutlu
- Saugata Ghose
- Mahmut Taylan Kandemir
- Rachata Ausavarungnirun
- Adwait Jog
- Christopher J. Rossbach
- Jayneel Gandhi
- Vance Miller
Citations in the corpus
- OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance (2013, background): “The minimum L2 miss latency is assumed to be 120 compute core cycles [56].”
- Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking (2018, background): “This has led to a prolific line of publications that shed light on instruction encoding [7, 8, 9], and memory hierarchy’s geometry and features [10] at each level.”
- Accel-Sim: An Extensible Simulation Framework for Validated GPU Modeling (2018, methodology): “Numerous works have done micro-benchmarking to characterize aspects of GPU architecture for Tesla GT200 [73], Fermi [37], Maxwell [34], and recently Volta [26].”
- MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency (2018, background): “Data demand requests from GPGPU applications generally have very high row buffer locality [15, 69, 143, 150], so a scheduler that cannot distinguish address translation requests from data demand requests effectively de-prioritizes the address translation requests, increasing their latency, and thus ”
- Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks (2017, background): “As a result, based on a 350 ns latency from the time the DMA engine requests data from GPU memory to the time it arrives at the DMA engine [59] and the 200GB/sec compression read bandwidth, the DMA engine needs a 70KB (200GB/sec×350 ns) buffer, shown as block “B” in Figure 9.”