An approach to low-power, high-performance, Fast Fourier Transform processor design

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HEAX: An Architecture for Computing on Encrypted Data (2019, background): “öppelmann et al. [60] have also proposed an architecture for YASHE scheme. Since ciphertexts are prohibitively large to be stored on on-chip memory, authors propose to leverage the idea of Cached-NTT [3, 4]. CachedNTT suggests formulating the NTT of large polynomials as many invocations of a ﬁxed co”
HEAX: High-Performance Architecture for Computation on Homomorphically Encrypted Data in the Cloud (2019, background): “Cached-NTT mini- mizes the number of times off-chip memory transactions are performed since the off-chip memory access is significantly costlier compared with on-chip memory access.”
Accelerating Homomorphic Evaluation on Reconfigurable Hardware (2015, methodology): “The general idea of the cached-FFT algorithm [2,3], as visualized in Fig.”
A generalized cached-FFT algorithm (2005, methodology): “First fully described in 1999 [1], the cached-FFT algorithm has been used to develop at least three custom FFT processors: a 1024-point FFT chip [2], a 512-point 2D FFT chip [3], and a programmable 64–2048-point FFT chip [4].”