A Primer on Memory Consistency and Cache Coherence
By D. Sorin, Mark D. Hill, David A. Wood. Synthesis Lectures on Computer Architecture, 2012
365 citations recorded by the source corpus.
Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies
Subfields: Computer Networks and Communications, Hardware and Architecture, Information Systems
View Paper: https://www.semanticscholar.org/paper/10f1faeec4ee2158b8535b249a20de5419998153
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
In Hardware and Architecture
In Information Systems
Citations in the corpus
- InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (2018, background): “A memory consistency model (or memory model) specifies the order in which memory operations are performed by a core, and are observed by other cores, in a shared-memory system [10].”