A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

By I. Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy. IEEE Journal of Solid-State Circuits, 2009

471 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/0f3dcc8a28e23a7b413f6e2136ef86664051daaf

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In Electrical and Electronic Engineering

1. Massimo Alioto

Citations in the corpus

• Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial (2012, background): “The 10T cell in [61] solves this problem by adding a write wordline distributed by columns, which adds to the row wordline, thereby over-writing only the cell at the intersection between the two wordlines (instead of all cells within a row at a time).”