Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times

By Kihwan Choi, R. Soma, Massoud Pedram. Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004

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Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits (2005, background): “To deal with this, systems may exploit dynamic voltage scaling to allow the lowest VDD necessary to meet the circuit speed requirements while saving the energy used for the computation [1][5].”
Energy Conscious Scheduling for Distributed Computing Systems under Different Operating Conditions (2011, background): “In [22], [23], [24], power-performance trade-offs are studied for (sequential) applications with non/soft-real-time deadlines.”
Energy Harvesting for Structural Health Monitoring Sensor Networks (2008, methodology): “While slowing down the CPU with DVS can provide quite a bit of power savings, applying DPM typically increases the savings by at least a factor of 10, and in many systems by significantly more than that.”
A dynamic compilation framework for controlling microprocessor energy and performance (2005, methodology): “Existing hardware or OS time-interrupt based DVFS techniques typically monitor some system statistics (such as issue queue occupancy [22]) in fixed time intervals, and decide DVFS settings for future time intervals [7, 19, 22, 23].”