XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks
By Zhewei Jiang, Shihui Yin, Mingoo Seok, Jae-sun Seo. 2018 IEEE Symposium on VLSI Technology, 2018
454 citations recorded by the source corpus.
We present an in-memory computing SRAM macro that computes XNOR-and-accumulate in binary/ternary deep neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay product than digital ASIC, and also achieves significantly higher accuracy than prior in-SRAM computing macro (e.g., 98.3% vs. 90% for MNIST) by being able to support the mainstream DNN/CNN algorithms.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/03056f2c785b9073d1ef4487f24c24938d9cbf13
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In Electrical and Electronic Engineering
Citations in the corpus
- Hardware implementation of memristor-based artificial neural networks (2024, unknown): “3a for an example of the structure of a crossbar array of 6T SRAM) have been widely used for VMM 75 – 77 .”
- In-Memory Computing: Advances and prospects (2019, methodology): “FIGURE 7: An illustration of analog-computation nonidealities: (a) the BL/BLb-discharge nonideality in [7] and (b) the read-BL nonideality in [15].”