Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

By S. Barraud, M. Berthomé, R. Coquand, M. Cassé, T. Ernst, M. Samson, P. Perreau, K. Bourdelle, O. Faynot, T. Poiroux. IEEE Electron Device Letters, 2012

243 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/01287cfa01053fb511bbed7b7ef66e83aad3d64f

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1. Chitrakant Sahu
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Citations in the corpus

• Charge-Plasma Based Process Variation Immune Junctionless Transistor (2014, methodology): “3 shows the calibration of our model parameters to the experimental SOI-JLT data [4].”